As is known in the art, a comparator circuit is a device that compares two input signals (either voltage or current) and provides an output digital signal that indicates which of the input signals is larger. FIGS. 1a-1c illustrate a comparator without hysteresis. FIGS. 1d-1h illustrate the structure and operation of a comparator with hysteresis. Generally, a comparator COMP 1 as shown in FIG. 1a has two input terminals Vin and Vth that are applied to a differential amplifier within the comparator COMP1. The voltage at the terminal Vth is the threshold voltage for determining whether the voltage at the input terminal Vin is lesser or greater than the threshold voltage level. When the voltage at the input terminal Vin transitions through the voltage level of the voltage at the terminal Vth, an output terminal Vo has a voltage representing the sign of the difference between the voltages applied to the two input terminals Vin and Vth. The input voltages must be each greater than the offset voltage of the differential amplifier plus an overdrive voltage such that the gain of the differential amplifier causes the voltage at the output terminal Vo to assume a voltage level defining a digital logic state VOH and VOL. FIG. 1b is a plot of the voltage at the input terminal Vin versus the voltage at the output terminal Vout. FIG. 1c is a plot of the voltage at the input terminal Vin and the voltage at the output terminal Vout versus time. If the voltage level at the input terminal Vin is relatively slow in its transition, any noise present at the input terminals Vin and Vth may cause multiple transitions of the voltage level at the output terminal between the digital states. In many applications, these multiple transitions may cause damage to devices being controlled such as motors, switches, etc.
A solution to prevent multiple transitions of the comparator COMP1 is circuit is the addition of hysteresis to the comparator COMP1. Hysteresis introduces two separate threshold voltage levels to the comparator COMP1. FIGS. 1e and 1g are a schematic for a comparator with hysteresis. In FIGS. 1e and 1g, a voltage divider is added from the positive terminal +. The voltage divider is formed of the resistors R1 and R2. FIGS. 1e and 1h are plots of the input voltage Vin versus the output Vo of the comparator COMP1 for the comparators of the FIGS. 1d and 1g. In FIG. 1g, a first terminal of the resistor R1 is connected to receive the threshold voltage level Vth. A second terminal of the resistor R1 is connected to the first terminal of the resistor R2 and to the positive terminal of the comparator COMP1. The second terminal of the resistor R2 is connected to the output terminal of the comparator COMP1. In FIG. 1e, the output voltage terminal Vo is at the high output voltage level, when the input terminal Vin is at a voltage level less than the high threshold voltage level VthH when the input voltage level is transitioning from a lower voltage level to a higher voltage level. When the input voltage level passes the higher threshold voltage level VthH, the output voltage level is forced to the lower voltage VoL. When the input voltage level is greater than the lower threshold voltage level VthL, the output voltage is at the lower output voltage level VoL. When the input voltage is transitioning from a voltage greater than the lower threshold voltage level VthL to a voltage level less than the lower threshold voltage level VthL, the output voltage level is forced to the higher output voltage level VoH at the input voltage level reaching the lower threshold voltage level VthL. If there is noise on the negative(−) input voltage terminal Vin or the positive (+) input voltage terminal, the comparator will not have returned to the lower threshold level VthL, if the noise is not greater than the higher threshold voltage level VthH.
FIGS. 1g and 1h have the input voltage Vin and the threshold voltage Vth exchanged. In that case, as shown in FIG. 1h, the directions for the transitions of the input voltage level Vin to the positive (+) terminal of the comparator COMP1 versus the threshold voltage levels VthL and VthH are reversed from those of FIG. 1e. Similarly, the output voltages VoL and VoH versus the input voltage Vin are reversed.
The comparators COMP1 illustrate two types of hysteresis, where classically hysteresis is by changing the threshold voltage levels VthL and VthH dependent on the state of the output voltage levels VoL and VoH. Most means of doing this in the prior art comparators add at least 5 mV to the switching threshold voltage levels VthL and VthH.
In the prior art, other ways to achieve dynamic hysteresis often act on the inputs themselves by pulling the input threshold voltage levels VthL and VthH apart once the output changed state.
An application for a comparator is in a buck DC-to-DC converter. The comparator compares the output voltage of the buck DC-to-DC converter with a reference voltage and determines if additional current needs to be applied to an inductor in the circuit as is known in the art. The switching frequency of the current to the inductor or from the inductor are generally fixed with the duty cycle of the switching frequency being adjusted or pulse width modulated to determine the amount of current flowing into the inductor and thus to the load circuit connected the output terminal of the DC-to-DC converter.
Generally, buck DC-to-DC converters operate in one of two different modes, a continuous mode and a discontinuous mode. When the buck DC-to-DC converter is operating at light load (a small load current), the current supplied from the supply voltage source is not supplied on each cycle and the current then supplied from the collapsing field of the inductor. Instead of being a pulse width modulated (PWM) conversion process in the continuous mode, the conversion in now based on a pulse frequency modulation (PFM) in the discontinuous mode. Often the discontinuous mode is used in portable electronics such as smart cellular telephone, tablet computers, digital reader, etc. as a “sleep mode”. The only current required by the system in these applications is monitoring current for system maintenance (i.e. system clocking and timers, cellular network monitoring, wireless network monitoring).
The decision to move between continuous or synchronous mode and the discontinuous or sleep is taken based on the output current of the buck DC-to-DC converter to the system load. This decision to switch between modes is made using a comparator. To prevent the comparator from toggling between the synchronous and the sleep modes, hysteresis is required. Typically hysteresis is implemented using a small voltage offset in the comparator, as described above. Many variations of these methods exist to perform the voltage offset hysteresis.
The buck DC-to-DC converter estimates the output current by measuring the voltage drop across a PMOS pass-device that is connected between the supply power source and the inductor to supply current to the inductor. The PMOS pass device is activated to connect the supply power source during the positive phase of the switching waveform, and the load current is supplied through it.
The voltage drop across PMOS pass transistor is referenced to the supply power source and is proportional to the output current. This is then averaged in one of several ways to give a voltage that is proportional to the average output current.
The typical threshold current at which the decision must be made is not large, typically around 100 mA in various applications. The impedance of the PMOS pass transistor is designed to be very small, typically less than 100 mOhms, to give high efficiency. The voltage drop across PMOS pass transistor is therefore relatively small at approximately ˜10 mV as can seen from the above. This issue is further complicated in that the voltage across the PMOS pass transistor is typically scaled by the duty-cycle, and may be less than half this value ˜5 mV. Further, the decision to switch to the synchronous mode is made in sleep mode, where the quiescent current available to make this decision is very low. Therefore, no amplification is possible and the system used must be kept simple. So it can be seen that the voltage offset hysteresis is not adequate for the application as shown.